Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators
In IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, volume 70, number 1, pages 40-53, Jan/2023.
In this paper, we propose a methodology for co-optimizing application specific neural network (NN) accelerators for accuracy and energy expenditure per inference. The architecture of the NN is co-optimized with the concrete ASIC implementation of the accelerator to provide reliable estimates of the energy efficiency. While not constrained to a specific application or NN accelerator architecture, the method is demonstrated on an application specific NN accelerator for the detection of atrial fibrillation in human electrocardiograms that is implemented in 22FDX/FDSOI technology. The NN accelerator is highly parameterizable, i.e., it can map NNs with different architectural properties to a synthesizeable register transfer level representation. The parameter space is further expanded by the parameters of the physical implementation (e.g. memories, clocking, voltage domains). Since the evaluation of accuracy and energy efficiency for a specific parameter combination is computationally expensive, different hyperparameter optimization methods are used and evaluated, including Bayesian Optimization, which tries to find the optimal neural network architecture and physical implementation parameters with a minimum number of training, simulation and evaluation steps.